1. Field of the Invention
The present invention relates to an output buffer circuit which is built in a semiconductor integrated circuit to yield an output signal of a predetermined level such as a high or low level in accordance with the level of the input signal.
2. Description of the Prior Art
FIG. 17 is a circuit diagram showing a conventional output buffer circuit, which is denoted generally by 100. Reference character A denotes an input signal which is applied to an input terminal; OE denotes an output enable signal which is applied to an output enable signal input terminal of the output buffer circuit 100; OUT denotes an output signal which is provided at the output terminal of the output buffer circuit 100; 101 denotes a P-channel transistor which functions as an output transistor for providing an high-level output signal; 102 denotes an N-channel transistor which functions as an output transistor for providing a low-level output signal; 103 denotes a NAND circuit; 104 denotes a NOR gate; and 105 and 106 denote inverters.
The operation of the prior art example will be described below in brief.
FIG. 18 is a graph for explaining the operation of the conventional output buffer circuit 100 depicted in FIG. 17. Upon input of the input signal A of the high-level to the input terminal when the output enable signal OE input to the output enable signal input terminal is high-level, the P-channel transistor 101 turns ON, and provides a high-level output signal OUT to the output terminal. Similarly, upon input of the input signal A of the low-level when the output enable signal OE is high-level, the N-channel transistor 102 turns ON, and provides a low-level output signal OUT.
In this instance, since the driving power of each of the P- and N-channel output transistors 101 and 102 is constant, a change in the load capacitance connected to the output terminal causes a change in the time in which the potential of the output signal from the output terminal reaches a predetermined high or low level. For example, as depicted in FIG. 1, when the load capacitance connected to the output terminal increases, the time for the potential of the output signal OUT to reach the high level becomes longer because of the fixed driving power of the P-channel transistor 101.
With the driving power of each output transistor heightened to solve this problem, however, when the load capacitance is small, the potential of the output signal OUT sharply changes to a predetermined level--this gives rise to a problem that an overshoot or undershoot of the output signal OUT is not suppressed. On the other hand, lowering of the driving power of the output transistor causes the problem of an increase in the time for the potential of the output signal OUT to reach a predetermined level when the load capacitance is larger.
FIG. 19 is a circuit diagram showing another conventional output buffer circuit, indicated generally by 110, which is identical in construction with the FIG. 17 example except that a capacitance C is connected between a node interconnecting gates of the P- and N-channel transistors 101 and 102 and the output terminal. Shown below the output buffer circuit 110 is its equivalent circuit with the output enable signal OE at the high level.
The output buffer circuit 110 of FIG. 19 is so configured as to settle the problem that the output buffer circuit 100 of FIG. 17 encounters. That is, the capacitance C is used to detect the potential at the output terminal. For example, when the potential of the output signal OUT varies, the potential is fed back to the gates of the P- and N-channel transistors 101 and 102 via the capacitance C. Accordingly, when the load capacitance connected to the output terminal changes in magnitude, the potential of the output signal OUT is transferred to the P- and N-channel transistors 101 and 102 via the capacitance C to control their operation and hence control the driving power of the output buffer circuit 110.
FIG. 20 is a block diagram depicting an input/output circuit in which there is incorporated the output buffer circuit 110 of FIG. 19. Reference numeral 110 denotes the output buffer circuit depicted in FIG. 19; 111 denotes an input buffer circuit; A denotes an input signal to an input terminal; OE denotes an output enable signal; Y denotes an output signal at an output terminal; IE denotes an input/output enable signal; and INOUT denotes an input/output circuit In the input/output circuit of FIG. 20, even when the output enable signal OE is not at the high level indicating that the output buffer circuit 110 is in the output state, that is, even when the output enable signal OE is low-level, a potential change at the input/output terminal INOUT triggers turning ON of the P- or N-channel transistor 101 or 102 via the capacitance C, leading to a malfunction.